An SRAM (Static Random Access Memory) cell is shown in FIG. 1. FIG. 1 schematically illustrates an SRAM cell 10. The SRAM cell 10 comprises first and second drivers N1 and N2. Illustratively, the drivers N1 and N2 are pulldown NMOS devices. The source 12 of N1 and the source 14 of N2 are connected to a reference voltage Vss which, for example, is ground. The drain 16 of N2 is connected to the gate 18 of N1. The drain 20 of N1 is connected to the gate 22 of N2. The SRAM cell 10 of FIG. 1 also comprises two load devices L1 and L2. The load devices L1 and L2 each have one terminal 24, 26 connected to a reference voltage Vcc and another terminal 28, 30 connected to the drains 20, 16 of N1 and N2, respectively. The reference Vcc is positive with respect to Vss.
The SRAM cell 10 also comprises two additional NMOS devices Mx and My. The devices Mx and My are pass transistors. The gates 32, 34 of Mx and My are connected to a wordline whose signal value is designated WORD. The sources 36, 38 of Mx and My are connected to bit lines 33, 35 whose signal values are designated BL and BLB (BL complement), respectively. The drains 40, 42 of Mx and My are connected the drains 20, 16 of N1 and N2, respectively. The bit lines 33, 35 are connected to the reference voltage Vcc via the NMOS devices M1, M2. The signals BL and BLB are applied to the bit lines 33 and 35 by applying appropriate signals to the gates of M1 and M2, respectively.
To write the cell, DATA (logic "1" or logic "0") is placed on the BL line 33 and DATAB is placed on the BLB 35 line. Then WORD is asserted. A read operation commences by precharging the BL and BLB lines. The WORD signal is asserted and either the BL or BLB line will be discharged by one of the pull down transistors N1 or N2.
The current path of the SRAM cell of FIG. 1 is indicated by the path 39 (or 41). The current path is along the bit line 33 (or 35), through Mx (or My), and through the driver N1 (or N2) to ground.
The purpose of the load devices L1 and L2 is to counteract the effect of charge leakage at the drains 20, 16 of N1 and N2. The load devices L1 and L2 may be polycrystalline silicon resistors or PMOS devices. In the case where L1 and L2 are PMOS devices, the sources of the PMOS devices are connected to Vcc; the drains of the PMOS devices are connected to the drains 20, 16 of N1 and N2. The gates of the PMOS devices L1, L2 are connected to the gates of the NMOS pull down driver devices N1, N2, respectively.
To reduce the size of the SRAM cell 10 and for use in advanced applications, where higher density and lower standby power is required, the load devices L1 and L2 may be implemented as thin film transistor (TFT) PMOS devices. In this case, the SRAM cell is known as a TFT SRAM cell.
A conventional SRAM array is shown in FIG. 2. FIG. 2 shows an m x n array 50 of memory cells 52 of the type shown in FIG. 1. The array of cells is organized into rows and columns. The columns are designed CL.O slashed., CL1, . . . , CLn. Each column has two bit lines associated with it. These bit lines are designed BL.O slashed., BLB.O slashed., BL1, BLB1; . . . ; BLn, BLBn. The bit lines are connected to Vcc by the NMOS devices M1.sub..O slashed., M2.sub..O slashed., M1.sub.1, M2.sub.1, . . . , M1.sub.n, M2.sub.n. The bit lines are precharged for a read operation using the NMOS devices M1, M2. For a write operation DATA and DATAB signals are placed on the bit lines via write buffer circuitry of the column select transistors M3-M6. These column select transistors will be described in greater detail below with reference to FIG. 3. Each row of cells has a wordline WL.O slashed., WL1, . . . , WLk. Each wordline has associated with it a wordline decoder 12-0, 12-1, . . . , 12-m which comprises the PMOS devices P5, P6 and the NMOS devices N5, N6.
A column CL from the array 50 of FIG. 2 is shown in greater detail in FIG. 3. In particular, FIG. 3 shows certain circuitry 60 associated with each column of the SRAM array in FIG. 2. However, for purposes of clarity, the circuitry 60 shown in FIG. 3 is only illustrated in connection with one such column. Column select circuitry 65 comprises select transistor pairs NMOS M4, PMOS M3 and PMOS M5, NMOS M6. Generally, to select a column, the column select signal Y.sub.0 is applied to transistors M4 and M6 and the column select signal Y.sub.0 B is applied to transistors M3 and M5.
Sense amplifier SA is coupled to bit lines BL and BLB of column CL0 along lines CDL (common data line) and CDLB, respectively. Further, one SA may be coupled to a plurality of columns since only one cell of one column will be read at any one time. As is known, sense amplifier SA functions during a read cycle of column CL, where SA determines the voltage difference between BL (BLB), which is established by the memory cell current, and load transistor M1 (M2) by outputing a logic `0` or `1`. Thus, during a read cycle, M1 and M2 serve as the bit line load to establish an appropriate read voltage potential.
The pass transistors of circuitry 60 include transistor pairs PMOS M7, NMOS M8 and PMOS M9, NMOS M10 located on bit lines BL and BLB, respectively. Coupled to common data lines CDL and CDLB are invertors I1 and 12 and NOR gates 13 and 14, respectively. Data input Din and write enable complement WEB signals are supplied to NOR gates 13 and 14.
Briefly, the operation of the write cycle begins when a data signal, logic `0` or `1`, is supplied to column CL from data input Din. Suppose a logic `0` from Din is to be written to bit line BL and the WEB signal is logic `0`. NOR gate 13 will output a logic `1`, while the inverter 11 will output a logic `0`. A logic `0` from the inverter, comprised of an NMOS transistor coupled to ground and a PMOS transistor coupled to voltage source Vcc (not shown), will turn on the NMOS transistor of 11. Thus, 11 will be driven low towards ground, which, in turn, will pull bit line BL low towards ground (Vss) as well.
On the other hand, bit line BLB will be pulled high since inverter 12, coupled to BLB, will be driven high to Vcc. 12 is driven high since NOR gate 14 will output a logic `0` activating the PMOS transistor coupled to Vcc (not shown). NOR gate 14 outputs a logic `0` since it receives a logic `1` from invertor 15 and a logic `0` from WEB.
However, although many techniques have evolved recently to speed up the SRAM data output in the SRAM column shown in FIG. 3, there has been relatively little effort to increase the write cycle speed which also affects the overall system performance. The speed of the write cycle in a column of an SRAM array is determined by the time it takes the bit line potential to be driven low towards ground.
One factor that decreases the speed of the write cycle includes the series resistance and switching times of the invertors 11, 12, the pass transistors M7-M10 and the select transistors M3-M6. This factor produces an R-C delay which slows the write cycle. Another factor that decreases the write cycle speed includes the inherent properties of the load transistors M1, M2 which tend to pull the bit line high. For example, when bit line BL is being written, load transistor M1 supplies a DC current on BL which drives BL high as the inverter I1 pulls BL low. Since the bit line is likely formed of metal having a resistance of a few hundred ohms, M1 acts as a resistor that builds up an IR (voltage) drop along BL. This is especially true when writing cells near the top of the column, i.e. the cells closest to M1.
Accordingly, it is an object of the present invention to provide an SRAM which has an increased write cycle speed and does not suffer from the short comings of the above-mentioned prior art SRAM schemes.